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TDA7448
6 CHANNEL VOLUME CONTROLLER
PRODUCT PREVIEW
s s s s s s
6 CHANNEL INPUTS 6 CHANNEL OUTPUTS VOLUME ATTENUATION RANGE OF 0 TO -79dB VOLUME CONTROL IN 1.0dB STEPS 6 CHANNEL INDEPENDENT CONTROL ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS
SO20 ORDERING NUMBER: TDA7448
DESCRIPTIO The TDA7448 is a 6 channel volume controller for quality audio applications in Multi-Channels Audio Systems Thanks to the used BIPOLAR/CMOS Technology, BLOCK DIAGRAM
2 50K IN2 19 50K IN3 3 50K IN4 18 50K IN5 4 50K IN6 17 50K GND CREF 11 20 VS SUPPLY 1 I2C BUS DECODER 10 9 12 SCL SDA ADDR 16 VOLUME OUT6 5 VOLUME OUT5 15 VOLUME OUT4 6 VOLUME OUT3 14 VOLUME OUT2 7 VOLUME
Low Distortion, Low Noise and DC stepping are obtained.
IN1
OUT1
D02AU1396
December 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TDA7448
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -10 to 85 -55 to 150 Unit V C C
PIN CONNECTION
VS IN1 IN3 IN5 OUT5 OUT3 OUT1 N.C. SDA SCL
1 2 3 4 5 6 7 8 9 10
D02AU1397
20 19 18 17 16 15 14 13 12 11
CREF IN2 IN4 IN6 OUT6 OUT4 OUT2 N.C. ADDR GND
THERMAL DATA
Symbol Rth j-pin Parameter thermal Resistance junction-pins Value 150 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max Input Signal Handling Total Harmonic Distortion V = 1Vrms f =1KHz Signal to Noise Ratio Vout = 1Vrms Channel Separation f = 1KHz Volume Control (1dB step) Mute Attenuation -79 90 Parameter Min. 4.75 2 0.01 100 90 0 0.1 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB
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TDA7448
ELECTRICAL CHARACTERISTCS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection 4.75 9 7 80 10 V mA dB
INPUT STAGE
RIN VCL SIN Input Resistance Clipping Level Input Separation THD = 0.3% The selected input is grounded through a 2.2 capacitor 35 2 50 2.5 90 65 K Vrms dB
VOLUME CONTROL
CRANGE AVMAX ASTEP EA Control Range Max. Attenuation Step Resolution Attenuation Set Error AV = 0 to -24dB AV = -24 to -79dB ET Tracking Error AV = 0 to -24dB AV = -24 to -79dB VDC Amute DC Step Mute Attenuation adyacent attenuation steps 0.5 -1 -2.0 -1 -2 -3 79 79 1 0 0 0 0 0 90 1.5 1 2.0 1 2 3 dB dB dB dB dB dB dB mV db
AUDIO OUTPUTS
VCLIP RL VDC Clipping Level Output Load Resistance DC Voltage Level THD = 0.3% 2 2 4.5 2.5 Vrms K V
GENERAL
ENO S/N SC THD Output Noise Signal to Noise Ratio Channel Separation left/Right Distortion AV = 0; VI = 1Vrms BW = 20Hz to 20KHz All gains = 0dB, Flat All gains = 0dB; VO = 1Vrms 80 10 100 90 0.01 0.1 15 V dB dB %
BUS INPUT
VIl VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Achnowledge VIN = 0.4V IO = 1.6mA 2.5 -5 0.4 5 0.8 1 V V A V
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TDA7448
Figure 1. Test circuit
0.47F IN1 IN1 2 50K 0.47F IN2 IN2 19 50K 0.47F IN3 IN3 3 50K 0.47F IN4 IN4 18 50K 0.47F IN5 IN5 4 50K 0.47F IN6 IN6 17 50K GND CREF 10F 11 20 VS SUPPLY 1 I2C BUS DECODER 10 9 11 SCL SDA ADDR 16 VOLUME OUT6 5 VOLUME OUT5 15 VOLUME OUT4 6 VOLUME OUT3 14 VOLUME OUT2 7 VOLUME
OUT1
D02AU1406
APPLICATION SUGGESTIONS The volume control range is 0 to -79dB, by 1dB step resolution. The very high resolution allows the implementation of systems free from any noise acoustical effect. CREF The suggested 10F reference capacitor (CREF) value can be reduced to 4.7F if the application requires faster power ON. Figure 2. THD vs. frequency
Figure 3. THD vs. R LOAD
Figure 4. Channel separation vs. frequency
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TDA7448
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7448 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 5. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 6. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 7. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
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TDA7448
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: s A start condition (S)
s s s s
A chip address byte, containing the TDA7448 address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P))
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge;
S = Start;
P = Stop;
A = Address;
B = Auto Increment
EXAMPLES No Incremental Bus The TDA7448 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
Incremental Bus The TDA7448 receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
DATA BYTES Address= 88 (HEX) (10001000): ADDR open; 8A (HEX) (10001010): connect to supply FUNCTION SELECTION: subaddress
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SUBADDRESS SPEAKER ATTENUATION OUT 1 SPEAKER ATTENUATION OUT 2 SPEAKER ATTENUATION OUT 3 SPEAKER ATTENUATION OUT 4 SPEAKER ATTENUATION OUT 5 SPEAKER ATTENUATION OUT 6 NOT USED" NOT USED
B=1: INCREMENTAL BUS; ACTIVE B=0: NO INCREMENTAL BUS X= DON'T CARE
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TDA7448
In Incremental Bus Mode, the three "not used" functions must be addressed in any case. For example to refresh " Speaker Attenuation 3 = 0dB and Speaker Attenuation 6 = -40 dB"; the following bytes must be sent:
SUBADDRESS SPEAKER ATTENUATION OUT 1 SPEAKER ATTENUATION OUT 2 SPEAKER ATTENUATION OUT 3 SPEAKER ATTENUATION OUT 4 SPEAKER ATTENUATION OUT 5 SPEAKER ATTENUATION OUT 6 XXX10010 XXXXXXXX XXXXXXXX 00000000 XXXXXXXX XXXXXXXX 00101111
SPEAKER ATTENUATION SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB SPEAKER ATTENUATION D0 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB
0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 1 0 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
-0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
value = 0 to -79dB and MUTE
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TDA7448
Figure 8. PIN:20 Figure 11. PINS: 10
VS
VS 20A 20K
CREF 20K
SCL
D96AU430
D96AU424
Figure 9. PINS: 5, 6, 7, 14, 15, 16
VS
Figure 12. PINS: 9
OUT1 to OUT6
24
20A SDA
20A
D96AU423
D02AU1398
Figure 10. PINS: 2, 3, 4, 17, 18, 19
VS 20A
IN
100K VREF
D96AU425
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TDA7448
Figure 13. Test and Application Circuit
J1 IN1 J2 OUT1
J3 C1 IN1 1 C3 IN2 2 C5 IN3 3 C7 IN4 4 C9 IN5 5 C11 IN6 6 C13 GND 7 10F 16V 20 + 8 13 + C14 100F 16V 0.47F 17 0.47F 4 0.47F 18 0.47F 3 0.47F 19 0.47F 2
IC1 IN1
TDA7448 C2 OUT1 7 22F 16V +
J4 1 OUT1
C4 IN2 OUT2 14
22F 16V + 2 OUT2
C6 IN3 OUT3 6
22F 16V + 3 OUT3
C8 IN4 OUT4 15
22F 16V + 4 OUT4
C10 IN5 OUT5 5
22F 16V + 5 OUT5
C12 IN6 OUT6 16
22F 16V + 6 OUT6
CREF
SCL
10
7
GND
N.C.
SDA
9
N.C. GND VS
ADDR
12
J5 1 JP1 R1 10 2 DGND VS
11
1
3 C15 0.1F 4 I2C R2 2 1 J6 1K R3 1K
SCL
SDA
VS
GND
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TDA7448
Figure 14. Component Layout (65 x 72mm)
Figure 15. PC Board (Component side)
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TDA7448
Figure 16. PC Board (Solder side)
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TDA7448
mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291
inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
0 1
SO20MEC
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TDA7448
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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